Current Issue : January - March Volume : 2016 Issue Number : 1 Articles : 4 Articles
Implementing compact, low-power artificial neural processing systems with real-time\non-line learning abilities is still an open challenge. In this paper we present a\nfull-custom mixed-signal VLSI device with neuromorphic learning circuits that emulate the\nbiophysics of real spiking neurons and dynamic synapses for exploring the properties of\ncomputational neuroscience models and for building brain-inspired computing systems.\nThe proposed architecture allows the on-chip configuration of a wide range of network\nconnectivities, including recurrent and deep networks, with short-term and long-term\nplasticity. The device comprises 128 K analog synapse and 256 neuron circuits with\nbiologically plausible dynamics and bi-stable spike-based plasticity mechanisms that\nendow it with on-line learning abilities. In addition to the analog circuits, the device\ncomprises also asynchronous digital logic circuits for setting different synapse and neuron\nproperties as well as different network configurations. This prototype device, fabricated\nusing a 180nm 1P6M CMOS process, occupies an area of 51.4mm2, and consumes\napproximately 4mW for typical experiments, for example involving attractor networks.\nHere we describe the details of the overall architecture and of the individual circuits and\npresent experimental results that showcase its potential. By supporting a wide range\nof cortical-like computational modules comprising plasticity mechanisms, this device will\nenable the realization of intelligent autonomous systems with on-line learning capabilities...
In recent years, software operating skills, the ability in computer literacy to solve problems using specific\nsoftware, has become much more important. A great deal of research has also proven that students� software\noperating skills can be efficiently improved by practicing customized virtual and simulated examinations.\nHowever, constructing these simulation-based examinations is cost intensive and time-consuming. Thus, a\nreconfigurable simulation-based test system designed on a proposed Software Operation-Finite State Machine\nhas been developed. Using this system, teachers can use a graphic authoring tool to construct and reconfigure\nsimulation-based tests for designated software operation tasks. For the students, these simulation-based tests can\nbe performed via the Web browser without any extra computer environment setting costs. After students finish\nthe test, the proposed system can automatically assess their online operating paths to generate the assessment\nreport for self-reflection. Moreover, in order to share and reuse the designed simulation-based tests, this paper\nsuggests some extensions of IMS Question & Test Interoperability to support the proposed simulation-based\noperation test format. Finally, an experiment was conducted to evaluate 38 sixth grade elementary school\nstudents. The experimental results show that this system can meet both teachers� and students� educational\nrequirements while significantly improving students� learning performance of the software operating skills....
FPGAs have shown several characteristics that make them very attractive for high performance computing (HPC). The impressive\nspeed-up factors that they are able to achieve, the reduced power consumption, and the easiness and flexibility of the design process\nwith fast iterations between consecutive versions are examples of benefits obtained with their use. However, there are still some\ndifficulties when using reconfigurable platforms as accelerator that need to be addressed: the need of an in-depth application study\nto identify potential acceleration, the lack of tools for the deployment of computational problems in distributed hardware platforms,\nand the low portability of components, among others. This work proposes a complete grid infrastructure for distributed high\nperformance computing based on dynamically reconfigurable FPGAs. Besides, a set of services designed to facilitate the application\ndeployment is described. An example application and a comparison with other hardware and software implementations are shown.\nExperimental results show that the proposed architecture offers encouraging advantages for deployment of high performance\ndistributed applications simplifying development process....
Photonic methods of radio-frequency waveform generation and processing can provide\nperformance advantages and flexibility over electronic methods due to the ultrawide bandwidth\noffered by the optical carriers. However, bulk optics implementations suffer from the\nlack of integration and slow reconfiguration speed. Here we propose an architecture of\nintegrated photonic radio-frequency generation and processing and implement it on a silicon\nchip fabricated in a semiconductor manufacturing foundry. Our device can generate\nprogrammable radio-frequency bursts or continuous waveforms with only the light source,\nelectrical drives/controls and detectors being off-chip. It modulates an individual pulse\nin a radio-frequency burst within 4 ns, achieving a reconfiguration speed three orders of\nmagnitude faster than thermal tuning. The on-chip optical delay elements offer an integrated\napproach to accurately manipulating individual radio-frequency waveform features without\nconstraints set by the speed and timing jitter of electronics, and should find applications\nranging from high-speed wireless to defence electronics....
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